Wednesday, 25. October 2017, UK, Arm Cortex processor behaviors Community
Event description
Prerequisites:
Introductory knowledge of either the A, R, or M profile of the Arm architecture.
Audience:
The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers.
Delivery Method:
Online
Length:
1 hour
Show more
Modules:
Introduction
Topic overview
Simple Sequential Model
Instruction fetching optimizations
Intro to instruction fetching optimizations
Branch prediction overview
Branch prediction method (return stack)
Branch prediction method (conditional branch prediction)
Effects of branch prediction
Data processing optimizations
Data processing optimizations - overview
Multiple execution pipelines
Speculative execution
Register dependencies
Cortex-A, R, and M interrupt behaviors
Data memory access optimizations
Data memory access optimizations - overview
Caching (cache eviction)
Caching (cache pre-fetching performance
Caching (cache maintenance - multi-caching)
Merging
Re-ordering overview
Re-ordering commands
ISB and DSB example
Barriers and speculative access
Summary
Cortex-A summary
Cortex-R summary
Cortex-M summary
Language: This course is presented in English.
Delivery Method: Bitesized video content
By booking this training course you accept our Terms and Conditions.
You will have 3 months access to this community.
Introductory knowledge of either the A, R, or M profile of the Arm architecture.
Audience:
The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers.
Delivery Method:
Online
Length:
1 hour
Show more
Modules:
Introduction
Topic overview
Simple Sequential Model
Instruction fetching optimizations
Intro to instruction fetching optimizations
Branch prediction overview
Branch prediction method (return stack)
Branch prediction method (conditional branch prediction)
Effects of branch prediction
Data processing optimizations
Data processing optimizations - overview
Multiple execution pipelines
Speculative execution
Register dependencies
Cortex-A, R, and M interrupt behaviors
Data memory access optimizations
Data memory access optimizations - overview
Caching (cache eviction)
Caching (cache pre-fetching performance
Caching (cache maintenance - multi-caching)
Merging
Re-ordering overview
Re-ordering commands
ISB and DSB example
Barriers and speculative access
Summary
Cortex-A summary
Cortex-R summary
Cortex-M summary
Language: This course is presented in English.
Delivery Method: Bitesized video content
By booking this training course you accept our Terms and Conditions.
You will have 3 months access to this community.
Arm Cortex processor behaviors Community , UK event
Source: Eventbrite
Eventhint.com is not a host of this event! Contact organizers here.
Eventhint.com is not a host of this event! Contact organizers here.